Semiconductor devices typically use discrete devices, such as metal oxide semiconductor (MOS) transistors as switching devices. Accordingly, in order to improve characteristics of semiconductor devices, high performance MOS transistors may be needed. As semiconductor devices become more highly integrated and operate at higher speeds, various approaches have been implemented to improve characteristics of these devices. In particular, since electron mobilities and holes (carriers in a channel of the MOS transistor) may directly affect drain current and switching characteristics, these factors may be considered in order to provide highly integrated, high speed semiconductor devices.
The carrier mobility in the channel of a MOS transistor may be improved by reducing the length of the channel or the thickness of the gate insulating layer. However, reduction in the channel length may result in a short channel effect, and a more complicated, expensive photolithography process may be used. Furthermore, reduction in the thickness of the gate insulating layer may result in an increase in leakage current through the gate insulating layer, causing a deterioration in device performance.
Other approaches for improving the carrier mobility in the channel include intentionally exerting compressive stress or tensile stress on a silicon substrate where the channel is subsequently formed. Details with respect to this approach are discussed, for example, in U.S. Pat. No. 6,562,703. As discussed therein, tensile strain is generated on a surface of a silicon layer by interposing a silicon germanium layer having a lattice constant larger than a silicon lattice constant between a silicon substrate and the upper silicon layer. Although the electron mobility in the tensile-strained silicon layer may be improved, the hole mobility may be detrimentally affected. In other words, although performance of an NMOS transistor may be improved, performance of a PMOS transistor may deteriorate.
Methods of improving electron mobility of an NMOS transistor as well as controlling decrease in hole mobility of a PMOS transistor is discussed in, for example, an article entitled A 90-nm Logic Technology Featuring Strained-Silicon (IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 51, No. 11, p1790, November 2004) by Thompson et al. As discussed therein, methods of forming a silicon nitride layer having high compressive stress as a stress layer on the NMOS transistor and PMOS transistor and reducing a thickness of the silicon nitride layer on an upper portion of the PMOS transistor. The silicon nitride layer is used as an etch stop layer in a subsequent contact structure formation process. In this case, it may be possible to improve electron mobility of the NMOS transistor as well as to control the decrease in hole mobility of the PMOS transistor. As the thickness of the silicon nitride layer on the upper portion of the PMOS transistor decreases, compressive stress of the silicon nitride layer on the upper portion of the PMOS transistor may also decrease. Accordingly, tensile stress exerted on the PMOS transistor may be reduced, such that the decrease in hole mobility can also be reduced. However, a problem may occur during the subsequent contact structure formation process. In particular, a contact hole is formed by forming an interlayer insulating layer on the silicon nitride layer and anisotropically dry-etching the interlayer insulating layer and the silicon nitride layer. Since the silicon nitride layers formed on the upper portions of the NMOS transistor and PMOS transistor have different thicknesses, defective openings may occur in the NMOS transistor, and over-etching may occur in the PMOS transistor. Problems caused by over-etching may be more problematic where misalignment occurs during the contact hole formation.